1. Technical Field of the Invention
The present invention relates generally to electrostatic discharge (“ESD”) protection, and more particularly, to a silicon controlled rectifier (“SCR”) device for on-chip ESD protection.
2. Description of the Related Art
Integrated circuits (IC's) and other semiconductor devices are extremely sensitive to high voltages that may be generated by contact with an electrostatic discharge (“ESD”) event. As such, ESD protection devices are essential for integrated circuits. An ESD event generally results from the discharge of a high voltage potential of several kilovolts, and leads to pulses of high current of several amperes in a short duration of several tens of nanoseconds. An ESD event is generated within an IC by human contact with the leads of the IC or by electrically charged machinery being discharged in other leads of an IC. These electrostatic discharges may destroy the IC's during installation of the IC's into products.
ESD damage has become the main reliability issue for complementary metal-oxide-semiconductor (“CMOS”) integrated circuit (“IC”) products fabricated in nanoscale CMOS processes. On-chip ESD protection devices, such as n-type metal-oxide-semiconductor (“NMOS”) transistors, p-type metal-oxide-semiconductor (“PMOS”) transistors, field-oxide devices, diodes, parasitic bipolar junction transistors (“BJTs”), or silicon controlled rectifier (“SCR”) devices, must be added into CMOS chips to achieve required ESD robustness. Generally, an ESD protection device is initially kept at an off state in a CMOS IC. FIGS. 1A and 1B are schematic diagrams illustrating operation of an initial-off ESD protection device 10. Referring to FIG. 1A, ESD protection device 10, electrically connected between a pad 12 of an IC (not shown) and a reference voltage level, is initially kept off. When pad 12 is zapped by an ESD pulse, ESD protection device 10 is triggered on by the overstress ESD voltage to conduct an ESD current IESD from pad 12 to the reference voltage level. However, since the core circuits of the IC fabricated in nanoscale CMOS technology have relatively thin gate oxides, the initial-off ESD protection design may no longer be able to effectively protect the core circuits against an ESD event.
To protect core circuits of an IC with relatively thin gate oxides, the turn-on speed of an ESD protection device must be further enhanced. Furthermore, the trigger voltage of an ESD protection device must be reduced lower enough to quickly respond to an ESD event. Initial-on ESD protection devices have been proposed to effectively protect nanoscale-CMOS ICs from ESD events. FIGS. 2A, 2B and 2C are schematic diagrams illustrating operation of an initial-on ESD protection device 20. Referring to FIG. 2A, ESD protection device 20, electrically connected between a pad 22 of an IC (not shown) and a reference voltage level, is kept off during normal operation of the IC. Referring to FIG. 2B, however, ESD protection device 20 is turned on when the IC is floating. When pad 22 is zapped by an ESD pulse, ESD protection device 20, already at an on state, is able to quickly discharge ESD current IESD from pad 22 to the reference voltage level.
In nanoscale-CMOS IC products, on-chip ESD protection devices are required to provide robust ESD protection in limited layout area to save the chip size. Silicon controlled rectifiers (SCRs) have been used for on-chip ESD protection for their superior area-efficient ESD robustness. However, SCR devices may be disadvantageous in high trigger voltage (Vt1), slow turn-on speed, and even latch-up issue. Many efforts have been made to address the disadvantages of SCR devices. A low voltage-triggered SCR (“LVTSCR”) has been proposed to reduce the trigger voltage of SCR devices. An example of the LVTSCR can be found in U.S. Pat. No. 5,465,189 to Polgreen et al., entitled “Low Voltage Triggering Semiconductor Controlled Rectifiers.” Moreover, advanced circuit techniques, for example, gate-coupled, substrate-triggered and GGNMOS-triggered techniques, have been proposed to enhance the turn-on speed of SCR devices. An example of the gate-coupled technique can be found in “A Gate-Coupled PTLSCR/NTLSCR ESD Protection Circuit for Deep-Submicron Low-Voltage CMOS IC's” by Ker et al., one of the inventors of the present application, IEEE Journal of Solid-State Circuits, vol. 32, no. 1, pp. 38-51, January 1997. The substrate-triggered technique can be found, for example, in “Latchup-Free ESD Protection Design with Complementary Substrate-Triggered SCR Devices” by Ker et al., IEEE Journal of Solid-State Circuits, vol. 38, pp. 1380-1392, 2003. As to the GGNMOS-triggered technique, an example of which can be found in “GGSCR: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Submicron CMOS Processes” by Russ et al., Proc. of EOS/ESD Symp., 2001, pp. 22-31. The above-mentioned SCR designs, however, still use initial-off ESD devices, and therefore may not be fast enough to respond to an ESD event.
In order to further enhance the turn-on speed, a native-NMOS-triggered SCR (“NANSCR”) has been proposed to achieve more efficient ESD protection for nanoscale-CMOS ICs. An example of the NANSCR can be found in “Native-NMOS-Triggered SCR (NANSCR) for ESD Protection in 0.13-μm CMOS Integrated Circuits” by Ker et al., Proc. of IEEE Int. Reliability Physics Symp., 2004, pp. 381-386. In this NANSCR, a native device, referring to a semiconductor device of which the substrate is undoped, is used to assume the “initial-on” function. To keep such NANSCR in an off state during normal operation of an IC, an on-chip negative-bias generator may be required. Such an on-chip negative-bias generator has been proposed in “Design of Negative Charge Pump Circuit with Polysilicon Diodes in a 0.25-μm CMOS Process” by Ker et al., Proc. of IEEE AP-ASIC Conf., 2002, pp. 145-148. Since additional processes are required to fabricate the on-chip negative-bias generator, the NANSCR may have limitation in practical applications of general CMOS ICs.
It is therefore desirable to have an initial-on SCR device for on-chip electrostatic discharge (“ESD”) protection that has a low trigger voltage, fast turn-on speed and latch-up immunity. Furthermore, the initial-on SCR device may be implemented in CMOS processes without incorporating any native devices.